1. Field of the Invention
The present invention relates to a serial data input circuit incorporated for use mainly in a microprocessor having a serial data input-output port or in an integrated circuit for communication.
2. Description of the Prior Art
An input circuit for the serial data is a circuit through which, for example, a micro-processor or an integrated circuit for communication, fetches the serial data from the exterior and converts it into parallel data.
For example, such serial data input circuit of conventional construction is disclosed in the "Digital Signal Processor MN1901/MN1909 User's Manual" issued by Matsushita Electronic Co., which is shown in a block diagram in FIG. 1.
In the drawing, a reference numeral 1 designates an input signal line for serial data DATAIN to be introduced, the input serial data DATAIN being given to a shift register 7 through the input signal line 1 and once stored in the shift register 7, 2 designates an input signal line of a serial clock SCK so that the serial clock SCK is given to a serial port control circuit 11 through the input signal line 2 from the exterior of the processor incorporating therein the serial data input circuit, 3 designates an output signal line for a serial port (input) ready signal READY so that the serial port ready signal READY indicating that the serial data is in condition of enabling the input of serial data is outputted from a serial port control circuit 11 through the signal line 3, and 4 designates a signal line for a serial input control signal SINH. Through the signal line 4, the serial input control signal SINH for input control of serial data is introduced into the serial port control circuit 11.
The shift register 7 is given a serial clock SCK through the serial port control circuit 11, so that the input serial data DATAIN given from the signal line 1, while being shifted-in sequentially in unit of one bit with the serial clock SCK being as the shift clock, is stored in the shift register 7. The serial data once stored in the shift register 7, in this example, is transferred as parallel data of 16 bits to a receiving data buffer 21 and received thereby as input data through an I/O bus 12.
Also, a reference numeral 20 designates a transmitting data buffer. Data, when transmitted, is once stored in the transmitting data buffer 20 through the I/O bus 12 and thereafter stored as the parallel data of 16 bits in the shift register 7, the parallel data being outputted as output serial data DATAOUT to the exterior from an output signal line 19 through an output latch 24 sequentially one bit at a time by use of the serial clock SCK as the shift clock.
A serial port control register 22 stores therein the serial data to be introduced, that is, bit number of the input serial data DATAIN in other words, data length, given as 4-bit counter 23.
The 4-bit counter 23, when the 4-bit data indicating data length and stored in the serial port control register 22 as above-mentioned is initially set and the serial port control circuit 11 controls the shift resister 7 to start input of the input serial data DATAIN therein, decrements a count value one by one per one bit of the input serial data DATAIN to thereby give the value to the serial port control circuit 11.
Accordingly, the serial port control circuit 11, when it detects the count value of the 4-bit counter becomes zero, concretely, the 4-bit signal of the count value becomes a logical "0000", stops input of the input serial data DATAIN into the shift register 7, thereby controlling the input of serial data. When the output serial data DATAOUT is outputted, the operation is similar to the above.
FIG. 2 is a typical view showing the field of the serial port control register 22.
In the drawing, a reference numeral 25 is the field into which the data length (bit number) of the input serial data DATAIN or the output serial data DATAOUT is written, the field comprising four bits of STL0 to STL3 as abovementioned.
Also, an SON field 26, when a logical "1" is written therein, shows the start of use for the serial port, and at an SMOD field 27, when a logical "0", the end of serial data is recognized by the count value of the 4-bit counter 23 and, when a logical "1", it is recognized by the trailing edge of the serial input control signal SINH given from the exterior.
Such operation of the conventional circuit is as follows:
Data length of data to be transmitted and received is previously written in the fields STL0 to STL3 at the serial port control register 22. In a case where the field SMOD is a logical "0", when the serial input control signal SINH and serial port ready signal READY each are assumed to be a logical "1", so as to rewrite the field SON from a logical "0" to "1", values of the fields STL0 to STL3 are loaded on the 4-bit counter 23.
The input serial data DATAIN is introduced into the shift register 7 synchronizing with the serial clock SCK while being shifted one bit at a time and simultaneously the 4-bit counter 23 performs down-count of serial clock SCK.
When the number of pulse at an input signal line 2 is counted down to zero, the serial port control circuit 11 changes the serial port ready signal READY from a logical "1" to "0" to thereby inform to the exterior of end of data transfer.
Thus, the serial data of desired bit length in the range of 1 to 16 bits can be transferred. However, in a case where the field SMOD is a logical "1", when the serial input control signal SINH rises even before the count value of 4-bit counter 23 becomes a logical "0", the serial port ready signal READY is enforced to be a logical "0", so that the 4-bit counter 23 is forcibly cleared to stop the input of data.
In the aforesaid circuitry, the 4-bit counter 23 is required for counting the serial clock signal SCK and also the serial port control circuit 11 requires a circuit which detects that the count value of the 4-bit counter 23 is zero, that is, the value of 4-bit becomes a logical "0000". As a result, a problem is created in that the circuitry and control thereof are complicated and the member of components increases to thereby enlarge an occupied area when the data input circuit is laid out as an actual circuit on the chip.